1. Technical Field
The present disclosure relates to an LDMOS semiconductor device and to a manufacturing method thereof.
2. Description of the Related Art
As is known, some applications of power MOSFET devices (or power MOSFETs) use said power MOSFETs for being driven at high switching frequencies. An example is that of electrical switches used in the field of high-frequency pulse-width modulation (PWM). To maximize the efficiency of the device it is expedient for the dynamic performance to exhibit a negligible loss of power during switching operations. This condition is verified by minimizing the values of capacitance of the parasitic capacitors inside said devices. Particular attention is be paid to minimization of the gate-to-drain capacitance CGD, since said capacitance CGD determines the duration of the period of transient of the voltage signal during switching; it is thus of fundamental importance to minimize the value of capacitance CGD in order to minimize the power losses of the power MOSFET. A parameter that is strictly linked to parasitic capacitances and is typically used to characterize the efficiency of a power MOSFET in switching, is the gate charge QG; in fact, the value of gate charge QG provides an estimate of the amount of current that is be supplied to the gate terminal of the power MOSFET to obtain switching of the device from the OFF state (where it does not conduct electric current) to the ON state (where there is conduction of electric current between the source and drain terminals).
LDMOSs (lateral double-diffused MOSFETs) may advantageously be used in a wide range of frequencies, with powers that range from a few watts to some hundred watts. A classic LDMOS structure comprises a substrate that has, in lateral sectional view, a horizontal sequence constituted by a laterally diffused low-resistance area (of a P+ type and referred to as “sinker”), a source region, a gate region, and a lightly doped drain (LDD) that provides the drain terminal. The LDD region further faces a surface of the substrate. This structure of a known type forms, for obvious reasons, an elementary cell with a high “pitch”.
Lateral MOS transistors have been widely studied, and in the literature techniques are known for minimizing the internal capacitances and for obtaining values of drain-to-source ON-resistance (RDS_ON) comparable with the values of trench-FET technology.
FIG. 1 shows an LDMOS transistor of a known type, in particular described in U.S. Pat. No. 7,936,007. With reference to FIG. 1, illustrated therein is a lateral sectional view of a structure designed to minimize the pitch of the base cell of an LDMOS. In this case, an LDMOS transistor 1 includes a substrate 2 having a top surface 2a and a bottom surface 2b opposite to one another, where an LDD region 3 extends starting from the top surface 2a of the substrate 2 towards the bottom surface 2b (without reaching the bottom surface 2b). Present above the bottom surface 2b is a drain region 4. The LDD region 3 is obtained via formation, starting from the top surface 2a of the substrate 2, of implanted regions 5a and 5b, of an N type, self-aligned to the gate terminal 6 and set between two gate terminals 6 set alongside one another; a sinker region 7 extends into the substrate 2, adjacent to body regions 10 and underneath source regions 9. A conductive layer 8 extends over, and is electrically insulated from, the gate terminal 6, and penetrates into the substrate 2 until it contacts the source regions 9 and sinker regions 7.
To minimize the parasitic capacitance between the gate terminal 6 and the LDD region 3, the structure illustrated in FIG. 1 may be modified so that the conductive layer 8 extends over the side wall 6a of the gate terminal 6, above the LDD region 3. By connecting the conductive layer 8 to a reference ground terminal, a conductive “shield” is formed designed to attenuate the hot-carrier injection (HCl) phenomenon and improve the gate-to-drain decoupling. Furthermore, a dielectric layer should be provided for separating the portion of the conductive layer 8 that extends over the LDD region 3 from the top surface 2a of the substrate 2. This dielectric separation layer preferably has a thickness in the region of 100-200 nm. A solution that goes in this direction is the one described in U.S. Pat. No. 7,589,378 (not illustrated in the figures). This document proposes an LDMOS transistor with surface LDD region, in which a conductive shield extends over the gate terminal and alongside it, over the LDD region and separated from the latter by a dielectric layer. In this way, a reduction of the electrical field is obtained, with consequent benefit in terms of increase in drain-to-source ON-resistance RDS_ON and attenuation of the value of gate-to-drain capacitance. As mentioned previously, the solution with surface LDD region imposes constraints on the minimum pitch that may be obtained, which may be further reduced only at the expense of the value of breakdown voltage, which is considerably reduced.
Alternatively, more complex processes may be adopted, of the type described in U.S. Pat. No. 7,829,947, where a power LDMOS has a region of field oxide under the gate region to minimize the capacitance between the gate region and the LDD region. The above device, however, is extremely difficult to manufacture as regards controlling superposition between the LDD region and the gate region.
FIG. 2 shows a cross section of an elementary cell of a power device according to a further embodiment of a known type, described in US Patent Publication No. 2014/0197487, filed in the name of STMicroelectronics S.r.l.
The device 20 of FIG. 2 is an electronic semiconductor device and comprises a semiconductor body including a substrate 23 (with N+ doping) and an epitaxial layer 16 (with P− doping). A body region 14, with P doping, extends into the epitaxial layer 16, and a source region 17, with N doping, extends into the body region 14. The region 18, within the body region 14 and electrically coupled to the source region 17, is an enrichment region, with P+ doping. A drain region 19, with N doping, extends vertically into the epitaxial layer, alongside the body region 14 and is electrically coupled to a back metallization 13 through the substrate 23. A gate electrode 11 extends over the epitaxial layer 16 between the source region and the drain region 19.
A first trench 12 extends through the epitaxial layer and houses a trench dielectric region 12a (for example, comprising a plurality of dielectric layers) and a first trench conductive region 12b within the trench dielectric region. A second trench 15 extends through part of the epitaxial layer 16 within the body region 14 and terminates in the body region 14. The second trench 15 houses a second trench conductive region 15a in electrical contact with the body region 14 and with the source region 16. As has been said, the drain region 19 extends through the epitaxial layer 16 until it reaches and contacts the substrate 23, and is set between, and in direct contact with, the body region 14 and the trench dielectric region 12a. The first and second trench conductive regions are further electrically coupled to one another and to a ground reference terminal by a metallization 21.
The device of FIG. 2 enables minimization of the parasitic internal capacitances, reducing the gate charge QG, and consequently enables a good value of figure of merit (FOM) for being obtained. The specific drain-to-source ON-resistance RDS_ON is kept at relatively low values thanks to the high doses of LDD used. This solution makes it possible to obtain a fast device at the expense of area occupied.